![]() T1GSS T1G TMR1GE disabled T1GTM disabled T1GPOL low T1GGO_nDONE done T1GSPM disabled T1CKPS 1:1 T1SOSC T1CKI_enabled T1SYNC do_not_synchronize TMR1CS External TMR1ON off Set the Timer to the options selected in the GUI LFOEN disabled ADOEN disabled SOSCEN enabled EXTOEN disabled HFOEN enabled CSWHOLD may proceed SOSCPWR Low power SOSCBE crystal oscillator #pragma config CPD = OFF // Data NVM Memory Code Protection bit->Data NVM code protection disabled #pragma config CP = OFF // User NVM Program Memory Code Protection bit->User NVM code protection disabled #pragma config LVP = ON // Low Voltage Programming Enable bit->Low Voltage programming enabled. #pragma config WRT = OFF // User NVM self-write protection bits->Write protection off #pragma config DEBUG = OFF // Debugger enable bit->Background debugger disabled #pragma config STVREN = ON // Stack Overflow/Underflow Reset Enable bit->Stack Overflow or Underflow will cause a Reset #pragma config PPS1WAY = ON // PPSLOCK bit One-Way Set Enable bit->The PPSLOCK bit can be cleared and set only once PPS registers remain locked after one clear/set cycle #pragma config BORV = LOW // Brown-out Reset Voltage selection bit->Brown-out voltage (Vbor) set to 2.45V #pragma config BOREN = OFF // Brown-out Reset Enable bits->Brown-out Reset disabled #pragma config LPBOREN = OFF // Low-power BOR enable bit->ULPBOR disabled #pragma config WDTE = OFF // Watchdog Timer Enable bits->WDT disabled SWDTEN is ignored #pragma config PWRTE = OFF // Power-up Timer Enable bit->PWRT disabled #pragma config MCLRE = ON // Master Clear Enable bit->MCLR/VPP pin function is MCLR Weak pull-up enabled #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable->Fail-Safe Clock Monitor is disabled #pragma config CSWEN = OFF // Clock Switch Enable bit->The NOSC and NDIV bits cannot be changed by user software #pragma config CLKOUTEN = OFF // Clock Out Enable bit->CLKOUT function is disabled I/O or oscillator function on OSC2 #pragma config RSTOSC = HFINT32 // Power-up default value for COSC bits->HFINTOSC with 2x PLL (32MHz) #pragma config FEXTOSC = LP // FEXTOSC External Oscillator mode Selection bits->LP (crystal oscillator) optimized for 32.768 kHz Any clues to what I've missed please? Code below Pete //CONFIG1 The only other input is RA2 using the base INT fucntion. Internal clock is 16Mhz I've used MCC for the initial config but noticed that it hadn't cleared the ANSEL bits when I only want A to D on AN0 and AN1 on RC0 and RC1. Note I know I could be using the prescaller to get the 1sec interrupt but in the past I'd fudged it by setting TM1H to 0x80 so I've stuck with that for now. Something I have working fine on the 16F1847. The external clock is to drive Timer 1 to inetrrupt on overflow every 1 sec. I've tried various cobimations of different examples of the same crystal type, 22pf and 33pf ceramic capacitors and values of RS (fig 6.3 of the data sheet) including a combination that works fine for a 16F1847. I'm trying to get a 32.768Khz crystal external Xtal on SOSCI and SOSCO using the default pins RA4 and RA5 (pins 2 &3). PIC 16F18346 External clock input to Timer 1
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